1. Technical Field
Embodiments of the present invention are related to the field of electronic devices, and in particular, to error reduction in electronic devices.
2. Description of Related Art
Single event upsets (SEUs), also referred to as soft errors (SERs), are radiation-induced transient errors in digital systems caused by high energy particles such as neutrons generated from cosmic rays and alpha particles from packaging material. Soft errors may be significant for microprocessors, network processors, high end routers and network storage components that target enterprise and applications with very high reliability, data integrity and availability. Bistables (latches and flip-flops) may be major contributors to the system-level soft error rate.
Scan Design-For-Testability (DFT) has become a de facto test standard in the industry because it enables an automated solution to high quality production testing at low cost. In addition, scan DFT may be used for post-silicon debug activities because it provides access to the internal nodes of an integrated circuit. Scan implementations in major high-end microprocessors involve significant circuitry and clock signals that are used only during post-silicon debug and production testing.
Referring to FIG. 1, a conventional pulse latch/scan cell 10 is shown for use in scan DFT. The latch/scan cell 10 includes a system pulse latch 12 and a scan circuit 14. The system pulse latch 12 is a single phase latch which stores (latches) a data input signal D based upon a clock pulse of a pulsed system clock signal PCK and generates a data output signal Q. The data input signal D enters the system pulse latch 12 during a brief transparency window defined by the rising and falling edges of the pulsed system clock signal PCK and is stored in the pulse latch 12 for the rest of the clock cycle. In an integrated circuit (IC), pulse latch/scan cells 10 are positioned at input and output nodes of combinational logic circuits.
The pulse latch/scan cell 10 has a test and a functional mode of operation. During the test mode, the scan circuits 14 are chained together to form a serial shift register (not shown). With respect to a given cell 10 at an input node of a combinational logic circuit (not shown), a signal SHIFT may be applied to a tri-state enable inverter 16 to allow a scan-in (SI) signal (test pattern) to be stored in a storage element (inverters 17 and 18) of the pulse latch 12 and applied via the output terminal Q to the downstream combinational logic circuit. Another cell 10 at an output node of the combinational logic circuit, in response to the pulsed system clock signal PCK, captures a system response to the test pattern on the input terminal for the data input signal D. The captured system response may be placed on the output terminal SO (becomes a scan-out signal) in response to applying the signal SHIFT to a second tri-state enable buffer 19. During the functional mode of operation, the signal SHIFT is in a low state; hence, the inverter 16 is turned off so that the scan-in signal SI does not disturb the normal latch operation. Therefore, the scan circuit 14 is essentially not used, although it occupies additional area and draw additional leakage power.